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Form of workJob Description
Background:IBM's Electronics Research team has a need for an Electrical Engineer highly experienced in the design and implementation of complex functions and solutions in FPGAs. Candidates must have an extensive knowledge of Verilog or VHDL; they must possess the skills and experience customizing and integrating third-party IP, executing timing driven synthesis, running simulations, and performing design validation. Strong candidates will have design experience or a proficient understanding of the PCIe or Interlaken interface standards.
Knowledge and fluency designing Xilinx FPGAs using the Vivado Design Suite is highly desirable.
Job Duties:
Job Duty 1 – Design (and implement) PCIe-to-Interlaken section of the Host FPGA Data Path. Interlaken is IP licensed from third-party.
Job Duty 2 - Work with ASIC team to implement Host FPGA Interlaken interface to the ASIC's Interlaken interface.
Job Duty 3 - Work with Software team and Electronics Design team to test and verify functionality of entire data path from the Front-end Host to the Interlaken interface on the Host FPGA.
Job Duty 4 – Validate full data path between the Front-end Host and the ASIC S-Tree is functioning as designed.
Job Duty 5 – Optimize design for performance improvements.
Job Duty 6 – Write technical documentation describing FPGA architecture, its functional blocks and the data flow to and from the Host and ASIC.
- Bachelor's or Master's degree in Electrical Engineering
- Minimum of 10 years' experience.
- Design an FPGA based on functionality requirements and third-party IP for standardized interfaces; Implement design in Verilog or VHDL, synthesize FPGA, achieve timing closure, debug FPGA's functionality in the system. (10 years)
- Understanding of PCIe and how the interface works; Understanding of Interlaken and how the interface works. (5 years)
- Experience working with high-speed serial communication protocols. Working with interfaces and logic blocks in different clock domains. Design of clock trees for high-speed serial protocols. (10 years)
- Design data structures and control mechanisms for transferring high-speed serial data between two protocols in different clock domains, i.e., queueing and/or buffer management. (10 years)
- Ability to work other design team which will interface with the FPGA or run Software using the FPGA logic. Build a collaborative relationship with other team members.
- Good communication skills, both written and verbal.
- Demonstrated success working on a complex, tightly scheduled next-generation design where others depend on your work to progress.
- Familiarity with Linux. Experience writing Python scripts.
- Other: Show initiative by reading data sheets, specifications and other technical documentation.
Other Skills Desired, Years in each skill, where applicable:
Experience working with remote team members.
Exhibit eagerness to shorten learning curve and engage team members early.
