Senior Fpga Simulation Engineer

Experience with Simulation Verification phase including design, development and delivery

Developing simulation Test methods, creating Simulation plans and maintaining simulation verification regression environments

Extensive experience with System Verilog & UVM Methodology

In-depth understanding of Components of UVM verification environment including Virtual Sequences

DO-254 Process knowledge is desired

Experience with VHDL/Verilog simulations

Experience developing SystemVerilog Test bench environment, as well as test results and coverage reports

Knowledge of SystemVerilog assertions for coverage

Primary Skills:

Strong technical knowledge related to FPGA development and verification

Knowledge of chip architecture and design, FPGA tool flow, System Verilog, Python/Perl/Tcl, and debugging

Solid understanding of industry standard interfaces (e.g, DDR, PCI, I2C, UART and Ethernet, etc.)

Have familiarity with UVM Methodology

Have familiarity with DO-254 process