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Form of workJob Details:
Job Description:
Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing. Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools.
In this role you will be responsible for developing Extraction Runsets for one or more of the major EDA vendors on Intel's leading edge process nodes. This includes Synopsys ICV, Siemens Calibre, and Cadence Pegasus. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution.
#DesignEnablement
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 4+ years of experience or MS with 3+ years of experience or PhD degree with 1+ years of experience in EE/ECE or related field.
3+ years of experience in the following:
- DRC/LVS Runset Development in ICV-PXL or Calibre-SVRF or Pegasus language.
- EDA extraction tools - StarRC/Quantus/Calibre-xACT/xRC
- Perl, or Python or TCL.
1+ year of experience with CAD/CAE environments that involve circuit simulation, parasitic extraction, and netlisting tools.
Preferred Qualifications:
3+ years of experience in the following:
- PDK development.
- Experience in large scale software development, debugging, and support.
- Software development practices such as Agile and Test-Driven Development.
1+ year experience in the following:
- Physical design, layout, and verification flows.
- IC manufacturing process flows.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$139,480.00-$209,760.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing. Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools.
In this role you will be responsible for developing Extraction Runsets for one or more of the major EDA vendors on Intel's leading edge process nodes. This includes Synopsys ICV, Siemens Calibre, and Cadence Pegasus. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution.
#DesignEnablement
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 4+ years of experience or MS with 3+ years of experience or PhD degree with 1+ years of experience in EE/ECE or related field.
3+ years of experience in the following:
- DRC/LVS Runset Development in ICV-PXL or Calibre-SVRF or Pegasus language.
- EDA extraction tools - StarRC/Quantus/Calibre-xACT/xRC
- Perl, or Python or TCL.
1+ year of experience with CAD/CAE environments that involve circuit simulation, parasitic extraction, and netlisting tools.
Preferred Qualifications:
3+ years of experience in the following:
- PDK development.
- Experience in large scale software development, debugging, and support.
- Software development practices such as Agile and Test-Driven Development.
1+ year experience in the following:
- Physical design, layout, and verification flows.
- IC manufacturing process flows.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$139,480.00-$209,760.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
