Address
Form of workHello,
My name is Bhakti and I'm a recruiter at Artech, the #1 largest women-owned IT staffing firm in the US. We are constantly on the lookout for professionals to fulfil the staffing needs of our clients, and we currently have a Job opening that may interest you. Please find below, summary of the position.
If you are currently not in the job seeking market, feel free to refer this position to someone you may know to be a fit. However, should this position be of interest to you, please send me your resume or contact me directly at 9737861406.
Job Description:
Position: Circuit Design Engineer
Location: Lexington, MA
Duration: 36+ months (possible extension)
Job Description:
The client is seeking an experienced Layout and Mask Design Engineer to work on mask layout and PDK development for photonic integrated circuits (PICs), superconducting qubit and trapped-ion qubit quantum computing, and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which they should be fluent, and may have responsibility for the full layout project from pcell creation to final mask tapeout. The engineer should be familiar with both custom manual layout and automated scripted layout techniques, and in the development and support of process design kits (PDKs) for an in-house foundry. Key tasks will include coding layout pcells; writing technology files; laying out devices, test structures, systems, and full mask reticles; maintaining documentation and using revision control all in coordination with the broader layout and project teams. Experience with DRC and LVS is a plus but not required. Assignments will be somewhat complex in nature and good judgement and independent problem-solving abilities are required.
Requirements:
•Expertise with coding layout pcells in the Cadence Virtuoso (SKILL) environment
•Experience developing or supporting Process Design Kits (PDKs)
•Mask aggregation and layout
•Strong communication and team-based collaboration skills
•Ability to problem solve independently
Desired:
•Experience developing technology files and design environments in Cadence or similar tools: Experience with Cadence is preferred
•Experience with the Advanced Node version of Cadence
•Experience coding with Perl, TCL, or Python
•Integrated photonic or RF layout design experience
•Experience with Cadence CurvyCore a plus
Regards,
Bhakti Sharma
Associate Recruiter
Cell: +91- 9737861406
Email: bhakti.sharma@artech.com
360 Mt. Kemble Avenue, Suite 2000 | Morristown, NJ 07960
Website: www.artech.com
My name is Bhakti and I'm a recruiter at Artech, the #1 largest women-owned IT staffing firm in the US. We are constantly on the lookout for professionals to fulfil the staffing needs of our clients, and we currently have a Job opening that may interest you. Please find below, summary of the position.
If you are currently not in the job seeking market, feel free to refer this position to someone you may know to be a fit. However, should this position be of interest to you, please send me your resume or contact me directly at 9737861406.
Job Description:
Position: Circuit Design Engineer
Location: Lexington, MA
Duration: 36+ months (possible extension)
Job Description:
The client is seeking an experienced Layout and Mask Design Engineer to work on mask layout and PDK development for photonic integrated circuits (PICs), superconducting qubit and trapped-ion qubit quantum computing, and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which they should be fluent, and may have responsibility for the full layout project from pcell creation to final mask tapeout. The engineer should be familiar with both custom manual layout and automated scripted layout techniques, and in the development and support of process design kits (PDKs) for an in-house foundry. Key tasks will include coding layout pcells; writing technology files; laying out devices, test structures, systems, and full mask reticles; maintaining documentation and using revision control all in coordination with the broader layout and project teams. Experience with DRC and LVS is a plus but not required. Assignments will be somewhat complex in nature and good judgement and independent problem-solving abilities are required.
Requirements:
•Expertise with coding layout pcells in the Cadence Virtuoso (SKILL) environment
•Experience developing or supporting Process Design Kits (PDKs)
•Mask aggregation and layout
•Strong communication and team-based collaboration skills
•Ability to problem solve independently
Desired:
•Experience developing technology files and design environments in Cadence or similar tools: Experience with Cadence is preferred
•Experience with the Advanced Node version of Cadence
•Experience coding with Perl, TCL, or Python
•Integrated photonic or RF layout design experience
•Experience with Cadence CurvyCore a plus
Regards,
Bhakti Sharma
Associate Recruiter
Cell: +91- 9737861406
Email: bhakti.sharma@artech.com
360 Mt. Kemble Avenue, Suite 2000 | Morristown, NJ 07960
Website: www.artech.com
