Foundry Technology Development Staff Device Engineer

Job Details:
Job Description:
As the world's largest chip manufacturer, and a global leader in innovation and new technology, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.
What we offer:
We foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.
What we do:
At the heart of Intel's groundbreaking product advancements, the Logic Technology Development (LTD) organization is a powerhouse of process technology innovation. Our relentless pursuit of excellence and innovation propels Intel's IDM 2.0 strategy, ensuring that we not only meet but exceed the aspirations of our global customers. As we continue to lead the semiconductor industry, we are enhancing our technological capabilities to guarantee the triumph of our customers' diverse and ambitious projects.
Your Role in Intel's Foundry Revolution: As a Foundry Technology Development - Staff Device Engineer, you will be at the forefront of Intel's collaborative journey with our foundry partners. Your expertise will be pivotal in guiding our customers through the intricate journey of product development, starting from the critical design tape-out phase to the exhilarating moment of New Product Introduction (NPI) silicon qualification. You will play a vital role in overseeing the wafer manufacturing process and ensuring a seamless transition into volume production. This is a unique opportunity to be part of a team that is not just participating in the industry but actively shaping its future.
Learn more about our Amazing Benefits HERE
What you will do:

• Support product development on Foundry Technology aspects potentially intellectual property (IP) design activities and execution: design rules, mask tapeout, through High Volume Manufacturing (HVM).
• Engage side-by-side with Product Integration in New Product Introduction (NPI) execution such as wafer lot progress, skew split planning and targeting, device performance and variability analysis for customer products.
• Provide regular readouts and device reporting on process development progress and product health to management and external customers.
• Collaborate with Product Integration and Yield teams to assess and ensure compliance to customer technology metrics; spanning from fab process yield, E-Test (ET), Wafer Acceptance Criteria (WAC), performance, and process capability (CpKs).
• Lead investigations and root-causing on non-conformance for ET. May include scribeline test-structure design debug, GDS layout investigations and investigating on process deviations.
• Collaborate with Design Enablement and other teams to ensure the highest-quality Process Design Kit (PDK). May include examination of fab metrology, ET, and yield process data, silicon-to-simulation (Sil2Sim) comparison against variability targets and layout effect assessments.
• Work on Design Rule Check (DRC) Violations with the technology specific Waiver Review Board (WRB) stakeholders to assess risk of the violations.
• Support central TD factory teams to analyze and assess product yield and performance commits and Continuous Improvement Program (CIP).
• Execute to foundry customer service best practices, and improvements to fab and development operational systems and methodologies to improve efficiency and standardization in an expanding business opportunity.

Benefits:
We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs and amenities, time off, recreational activities, discounts on various products and services, and many more creative perks that make Intel a Great Place to Work.
Intel's approach for the future of work is grounded in our belief that our people are our most important asset. While we know we don't have all the answers for what will work best long-term, the data shows that many workers are looking for increased flexibility, and that's why we're leading with a hybrid-first approach. This is a hybrid position, with a possible remote option.
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Master's Degree with 5+ years of experience OR PhD Degree with 3+ years of experience. Accepted degrees in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline.
- Related work experience in one or more of the following fields:

• Semiconductor FinFET Technology device integration experience
• Foundry technology NPI silicon execution with split planning and skew lot deliverables
• Semiconductor yield engineering working on ET parametric related yield opportunities.
• Fabless design house in a foundry interfacing role.

Preferred Qualifications:

• PhD degree in Electrical Engineering, Materials Science, Chemical Engineering, Chemistry, Physics or related field.
• Exceptional communication and presentation skills of complex concepts, and solutions.
• Applied industrial experience in at least one of the following technical areas:
• Semiconductor process integration, device physics, logic, architecture and integration, and interconnect development on leading edge technology nodes.
• IC wafer fabrication process engineering, manufacturing systems, semiconductor materials, and wafer test (e.g. fabrication areas may include photolithography and advanced patterning, thin film deposition, planarization, defect metrology or spectroscopy).
• Trouble-shooting tape-out issues eg GDS Layout investigation and tracing and DRC errors investigation.
• Experience of analyzing product data including inline, e-test and SORT data; root cause investigations and driving for solutions. Knowledge on inline inspection method, electrical test structures and SORT programs.
• CP, CpK methodology, gap analysis and CIP activities to drive to closure.
• Process Design Kit (PDK) silicon model target generation, silicon-to-simulation correlation, test structure design, and electrical characterization.
• Device and ET parametric analysis with JMP Analytical Software and JSL scripting for data analysis.

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$123,139.00-$203,801.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.