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Form of workJob Description
Benefits:
Job Title: DFT Engineer
Job Location: Milpitas, CA
Description:
Primary Responsibilities:
Support and work closely with automotive customers (with special emphasis on in-system
test using LBIST MBIST) and non-automotive customers in defining DFT requirements and
specifications for the ASIC
Design and Verification of DFT logic and components
Generation of structural test vectors, analysis, and coverage improvement
Generation of timing constraints for the various DFT modes
Work with implementation teams on DFT STA, logical, physical, and power issues
Support ATE team with test vector porting, diagnosis, and physical failure analysis
Necessary Qualifications:
BS/MS in Electrical Engineering, Computer Science, or related field
Minimum of 10 years hands-on work experience in ASIC DFT design. Experience in an SoC
product development organization or in an ASIC vendor company along with customer
facing experience preferable
Hands-on experience with DFT circuit insertion and validation for scan, at-speed, MBIST and
Boundary scan
Experience with Industry standard DFT/ATPG EDA tools like Tessent/TestMax/Modus.
Experience with simulators and waveform debug tools.
Strong knowledge of DFT methodologies, industrial standards, and practices
Strong working knowledge of Chip design, Verilog/System Verilog, and design verification
Experience with STA tools like Primetime, SDF generation and Gate-level simulations
Understanding and expert handling of Verilog HDL based Netlists, design libraries and
Scripting (Perl/Tcl)
- 401(k)
- 401(k) matching
- Dental insurance
- Health insurance
- Paid time off
- Relocation bonus
- Tuition assistance
- Vision insurance
Job Title: DFT Engineer
Job Location: Milpitas, CA
Description:
Primary Responsibilities:
Support and work closely with automotive customers (with special emphasis on in-system
test using LBIST MBIST) and non-automotive customers in defining DFT requirements and
specifications for the ASIC
Design and Verification of DFT logic and components
Generation of structural test vectors, analysis, and coverage improvement
Generation of timing constraints for the various DFT modes
Work with implementation teams on DFT STA, logical, physical, and power issues
Support ATE team with test vector porting, diagnosis, and physical failure analysis
Necessary Qualifications:
BS/MS in Electrical Engineering, Computer Science, or related field
Minimum of 10 years hands-on work experience in ASIC DFT design. Experience in an SoC
product development organization or in an ASIC vendor company along with customer
facing experience preferable
Hands-on experience with DFT circuit insertion and validation for scan, at-speed, MBIST and
Boundary scan
Experience with Industry standard DFT/ATPG EDA tools like Tessent/TestMax/Modus.
Experience with simulators and waveform debug tools.
Strong knowledge of DFT methodologies, industrial standards, and practices
Strong working knowledge of Chip design, Verilog/System Verilog, and design verification
Experience with STA tools like Primetime, SDF generation and Gate-level simulations
Understanding and expert handling of Verilog HDL based Netlists, design libraries and
Scripting (Perl/Tcl)
