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Form of workReality Labs focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta’s Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta’s Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art graphics, vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art graphics IPs.
- Work with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading graphics IP’s optimized for XR products and use-cases, defining verification methodologies for each of the different core IPs.
- Define, track, and lead the execution of detailed test plans for the different modules and top levels.
- Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
- Keep track of coverage metrics and bugs encountered and fixed.
- Implement self-testing directed and random tests.
- Work with FPGA/emulation engineers to perform early prototyping.
- Support hand-off and integration of blocks into larger SOC environments
- Support post silicon bringup and debug activities.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 5+ years of System Verilog OVM/UVM DV experience.
- Knowledge of Python, Perl, shell scripting.
- Knowledge with assertions (SVA) or others.
- Knowledge of digital ASICs design flows.
Preferred Qualifications:
- Masters in Electrical Engineering or Computer Science.
- Formal verification experience.
- C, C++ coding, debugging experience.
- Experience as a digital design engineer.
- Experience with low power design.
- FPGA implementation and debug experience.
- Experience in verification of numerical compute based designs.
About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
