Address
Form of workJob Details:
Job Description:
Component Debug Engineer focused on post-Silicon product design enabling and optimization. If you like solving challenging puzzles and deep diving into new domains - this position is for you. You will be part of Intel's center of excellence for Silicon design debug supporting many product segments ranging from server to client to mobile. This team resolves product quality and performance issues blocking products from meeting production requirements with a combination of design and manufacturing problem solving expertise, leveraging state of the art methodologies and tools. Component debug is a critical ingredient to Intel's strategy of enabling strong design debug support for our entire product portfolio and scaling it going forward. In addition to the qualifications listed below, the ideal candidate will also have: Verbal and written communication skills Hands-on Self-motivated Problem solver Organized person Ownership Mentality
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a bachelor's degree in electrical engineering, Computer Engineering, or a related field with 6+ years' experience -OR- a master's degree in electrical engineering, Computer Engineering, or a related field with 4+ years' experience.
Preferred Qualifications:
- Experience in Silicon debug
- DFT (Design for Test)
- Digital circuit design methodology
- Design structural and functional diagnosis tools and methods
- Scan and Array infrastructure
- Scan and Array insertion with Mentor/Synopsys tools
- Scan and Array Pre/Post Si validation, Si enabling and testing
- Design structural and functional diagnosis tools and methods
- Post silicon validation concepts/methods including:
- High Volume Manufacturing (HVM)
- Test flows including die level and package level testing
- Test stimulus and coverage approaches
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$102,120.00-$169,020.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
Component Debug Engineer focused on post-Silicon product design enabling and optimization. If you like solving challenging puzzles and deep diving into new domains - this position is for you. You will be part of Intel's center of excellence for Silicon design debug supporting many product segments ranging from server to client to mobile. This team resolves product quality and performance issues blocking products from meeting production requirements with a combination of design and manufacturing problem solving expertise, leveraging state of the art methodologies and tools. Component debug is a critical ingredient to Intel's strategy of enabling strong design debug support for our entire product portfolio and scaling it going forward. In addition to the qualifications listed below, the ideal candidate will also have: Verbal and written communication skills Hands-on Self-motivated Problem solver Organized person Ownership Mentality
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a bachelor's degree in electrical engineering, Computer Engineering, or a related field with 6+ years' experience -OR- a master's degree in electrical engineering, Computer Engineering, or a related field with 4+ years' experience.
Preferred Qualifications:
- Experience in Silicon debug
- DFT (Design for Test)
- Digital circuit design methodology
- Design structural and functional diagnosis tools and methods
- Scan and Array infrastructure
- Scan and Array insertion with Mentor/Synopsys tools
- Scan and Array Pre/Post Si validation, Si enabling and testing
- Design structural and functional diagnosis tools and methods
- Post silicon validation concepts/methods including:
- High Volume Manufacturing (HVM)
- Test flows including die level and package level testing
- Test stimulus and coverage approaches
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$102,120.00-$169,020.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
