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Form of workWe are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!
We are looking for an experienced candidate for the role of ASIC Package Design Lead in Teradyne's Silicon Technology Engineering group. As the technical expert and team lead, you will technically oversee and coordinate the many packaging and advanced packaging activities across Teradyne's business units.
Packages designs will be for complex full custom ASICs as well as exploring advanced packages like SiP and MCM. The Package Design Lead will work closely with lead semiconductor designers, signal/power integrity experts and coordinate the overall packaging effort ensuring technical product quality. Over time the role will evolve to include leading ambitious advanced packaging enabling technology efforts across technical domains.
Your broad packaging background will enable you to identify opportunities and drive packaging technical excellence and efficiency initiatives. These likely include standardizing Teradyne's ASIC packaging and advanced packaging design flows, identifying key tools, and working with best-in-class external suppliers and internal functions to successfully execute packaging efforts across Teradyne's business units.
This position requires someone comfortable with the many technical aspects of ASIC packaging and advanced packaging and who enjoys the challenge of leading integration driven innovations across geographically diverse teams in pursuit of the world's best ATE test equipment.
Must have:
Packaging design experience with high-speed digital signals (>10Gbps) or mmwave
Experience in signal integrity and power integrity finite element modeling (HFSS, ADS, Cadence, etc)
Demonstrated capability to technically lead a team, communicate effectively, and enhance team synergy as a key team member
Ideally has:
A broad range of experiences across the build to spec through build to print continuum
Knowledgeable in packaging reliability and testing
Experience with die stacking, HBM, and CoWoS or similar
Additional desired qualifications
Prior ATE experience is a plus
Prior management experience is a plus
A thorough understanding of semiconductor physics and various semiconductor processes is a plus
- A Bachelors in Electrical Engineering, Mechanical Engineering, Materials Science or Physics (advanced degree preferred)
- >5 years' experience technically leading packaging efforts, with demonstrated product successes and including hands-on PCB or MCM/SiP substrate design, layout, and simulation.
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