Analog Design Engineer

Job Description

Role and Responsibilities:

At Intel, we work every single day to design and manufacture silicon products as the fundamental building blocks that empower people's digital lives. Do you love contributing to cutting edge IP technology that are enabling Moore's law to the next chapter by connecting silicon Chiplets from different process nodes? Do you want to see your designs running in the flagship datacenter, client, networking, and FPGA SOC/SIP? Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross-functional teams to deliver IP solutions for products that impact customers' lives?

Intel's IPG Die to Die(D2D) team is looking for an experienced senior Analog Design Engineer to join the rapidly growing die to die interconnect (UCIe PHY) IP space for Intel's flagship datacenter/server/chipset/Networking/FPGA/IFS System In Package(SIP) designs.

Responsibilities will include but are not limited to:

• Responsibilities include analog micro-architecture, technology pathfinding, specification, analog circuit design, layout supervision, documentation, DFT and DFM of analog and mixed signal clock generation units, leading and mentoring of team members and active collaboration with colleagues and partners across different design disciplines such as logic, validation, and physical design.
• Minimal travel may be required.
• Analog clock design responsibilities may consist of but not limited to high performance, low jitter clocking/PLL/DLL/PI, transmitter, receiver, analog to digital and digital to analog converters, custom power supply networks and other elements necessary to design, verify and productize high performance analog and die to die interconnect solution.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor of Science degree in Electrical Engineering with 4+ years of general analog IC and/or mixed-signal design experience OR Master of Science degree in Electrical Engineering with 3+ years of general analog IC and/or mixed-signal design experience OR PhD in Electrical Engineering with 1+ year of general analog IC and/or mixed-signal design experience.

• Ability to work independently, analyze and making design trade-offs of analog building blocks at transistor level.
• Familiarity with Cadence analog IC design tools.

Preferred Qualifications:

• The analog and/or mixed-signal design experience should be preferably in high performance, high efficiency Serdes or DDRIO space.
• Experience providing guidance to more junior engineers.
• Good written and oral communication skills are extremely important.

Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, OR, Hillsboro; US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, MA, Hudson

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00

• Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

JobType

Hybrid