Senior Fpga Dsp Firmware Design Engineer

Description

The Electronic Warfare (EW) Division of Leidos is looking for a FPGA DSP Firmware Engineer to lead a design team to design, develop, simulate, and integrate challenging DSP FPGA designs and RF sensor systems based on given program requirements. The successful candidate will have a strong background in technical team leadership for Firmware Design, the ability to implement MATLAB algorithms in the FPGA and incorporate client feedback into firmware revisions.
Primary Responsibilities
* Lead a Firmware Design team to design, integrate and test challenging DSP FPGA designs for EW sensor systems.
* Evaluate a project's firmware needs, designing a firmware solution to meet project needs and be able to communicate that design to the program leadership.
* Develop and implement new firmware, debug firmware to ensure it functions properly, evaluate performance and troubleshoot as needed.
* Incorporate client feedback into firmware revisions, manage budgetary and time constraints.
* Keep the firmware team up-to-date on technological developments and industry best practices.
* Lead the design and development of innovative reconfigurable Software-Defined Radio (SDR) architectures, Sensor Systems, Data Acquisition, from Air/Space to Ground deployments for government agencies
* Analyze schematic diagrams for high-speed digital and/or analog circuitry in associated FPGA-centric systems.
* Develop and maintain requirements documents, engineering drawings and configuration management policies for FPGA project hierarchy.
* Develop project test plans and test procedures, provide test planning support, and assist in the execution of both lab testing and field testing.
* Conduct experimental tests on latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications for selecting next-generation components for deliverable systems.
* Some travel and work at remote sites for limited time periods may be occasionally required.
* Provide status reports to project managers and/or division production manager as required.

Basic Qualifications
* Active US government Top Secret clearance.
* Ability to work full time at facility site in Arlington, VA
* Experience with FPGA Integrated Design Environment tool sets such as Xilinx Vivado and Mentor Graphics ModelSim.
* Experience with latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale+, Intel Stratix-10, and Xilinx RFSoC.
* Proficiency in hardware descriptor languages, HDL (VHDL, Verilog) and/or MATLAB model(s).
* Ability to perform design constraints generation and verification as well as evaluate synthesis and timing performance reports.
* Hands on design and test experience with signal processing concepts such as FFTs, channelizers, digital filters, digital modulation, digital down/up-conversion, adaptive processing, etc and their implementation into new or existing modular HDL designs.
* Familiarity with common signaling standards, typical IP hard macros such as SERDES, PLLS, etc. and/or protocols such PCIe, JESD204B, LVDS, etc.
* Proficiency with hardware integration, test and debug tools (high-speed logic analyzers, scopes, spectrum analyzers, etc.)
* Bachelors in Electrical Engineering or Computer Engineering or similar field
* Minimum of 12 years of relevant experience with at least 2 years in a technical leadership position

Preferred Qualifications
* Experience writing test software in C/C++ or assembly language to validate design
* Experience with high-speed (> 20GHz) design techniques
* ARM or RISC-V embedded processor based SoC design experience
* Proven experience in the military/aerospace hi reliability electronic warfare product development, especially in the area of radiation hardened, space grade FPGA circuit card design,
* Subject matter expert in high-speed digital hardware, embedded firmware & software, and miniaturized high-performance systems for EW applications.
* Expertise in optimum thermal management for FPGA circuit card design for high altitude conduction cooled applications
* Ability to obtain TS/SCI clearance

While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.

The Leidos pay range for this job level is a general guideline onlyand not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.