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SalarySenior Design Verification Engineer
Remote (Pheonix, AZ)
Contract (W 2 Only)
Job Description:
M*_ust Have : Experience with UVM and System is a must requirement*_
Key Responsibilities:
- Verifying RTL implementation for complex digital blocks to ensure high quality
- Developing verification strategies for new features, plan volume validation and coverage strategies
- Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
- Working with designers to do coverage analysis and take necessary actions to meet coverage goals
- Integrate VIPs as needed
- Closely work with design teams to drive feature enablement
- Mentor junior engineers on the team
Required Experience:
- Working experience on PCIe, DMA and/or NVMe protocols required
- Knowledge of bus protocols like AXI/AHB desired
- Grounds-up development experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/or BFMs is required
- Strong understanding of simulation tools and knowledge of scripting languages like Perl, tcl or cshell
- Highly motivated, Self-starter individual with ability to work in a fast-paced team environment
- Experience with UVM and System is a must requirement
- Requirement's-based verification is Required
Preferred Experience:
- DO_254 Preferred
- Verification EDA tools: Synopsys tooling
- FPGA: Xilinx/Microsemi Ethernet and AXI-Lite/AXI protocols
- Requirements management tool: Doors
- Component-level verification -> Preferred but not required. The candidate would be working on block levels.
Job Type: Full-time
Salary: $60.00 - $70.00 per hour
Expected hours: 40 per week
Schedule:
- 8 hour shift
Experience:
- Design Verification: 3 years (Required)
- UVM: 3 years (Required)
- RTL implementation: 2 years (Required)
- DO_254: 1 year (Preferred)
- Aerospace: 3 years (Required)
Willingness to travel:
- 25% (Preferred)
Work Location: Remote
