Job description
- Lead teams in delivering complex digital IP’s, meeting schedule, area, power, and performance targets. - Collaborate in developing precise design specifications for digital control blocks. - Implement physical design ready blocks in System Verilog. - Collaborate with project leads to track progress and gauge tapeout readiness. - Work with DV teams to create verification plans. - Work with silicon validation team in developing lab validation and qualification plans.
Address
Austin, TX
