Ip Design Engineer

In this role you will work on a small team dedicated to IP architecture, design, and verification. As a member of the team you will be asked to architect and design new modules while working with multiple cross-functional teams including: Design Integration, Platform Architecture, Software Engineering, DFT, and Debug. You will write formal verification to prove the designs (when feasible). All designs will be written in SystemVerilog and will use SV simulations and SVA formal verification environments. You will run quality checkers (lint, CDC, RDC, etc...) and be expected to provide constraints and waivers when necessary. You will be asked to support the DV simulation team and the bring-up teams with the usage of new IP modules. All new designs are required to have documentation, example code (where relevant), and integration notes. Expect to give presentations to cross-functional teams on the new IP designs.