Ic Custom Analog Layout Engineer

IC Custom Analog Layout Engineer

Minneapolis, MN

4-5+ Months Contract

Experience in IC layout of high performance analog including block level and chip level layout requirements. Understanding of parasitic impact on circuit performance is a plus. Capable of top level floor planning with knowledge of transistor, resistor, and capacitor matching in 28 nm process.

A successful candidate will have the following skills:

• 7+ years minimum experience as an IC Layout Designer with strong analog / mixed signal layout skills.

• Extensive experience with Cadence tools is required. (Virtuoso, VXL/GXL, Assura, PVS, LDE, EAD, Calibre)

• Experience with 28 nm TSMC technology node.

• Possess necessary skill set to complete any assigned layout task without supervision.

• Strong Analog Layout design skills and capable of solving device matching, electro-migration, power distribution, latch-up, ESD and circuit area restrictions.

• Ability to debug and resolve LVS/DRC errors independently.

• Must be able to communicate effectively with circuit designers to understand their requirements and implement the requested layout.

• Ability to recognize different solutions while maintaining the team's methodologies.

• Ability to work in a team environment or independently as required.

• An appreciation of parasitic related issues and ability to layout circuits to minimize coupling issues

• Strong communication skills.

• Work at multiple levels of hierarchy, from macro level to top-level.

• Thorough understanding of high speed, low power and DFM layout issues a plus.

Manager notes.

• It is not a contract to hire position. (Contract only)

• It is 4 to 5 month in length.

• This person has to have HIGH SPEED CIRCUIT EXP. (5 gig and higher)

• Also has to know how power circuits run on chip because there is a lot of heat.

Please send your profiles to prem@w3global.com or call me @ 972-393-4404