High Level Synthesis Design Engineer

Job Description:

As an HLS Design Engineer, you will contribute to the core processor functionality that helps enable Celestials unique value proposition. You will collaborate with architects and a small team of Design Engineers to implement the specified algorithms and control structures using HLS, while simultaneously making performance, power, area and latency optimizations. Using the fast iteration times enabled by HLS you will often evaluate a range of possible implementations before choosing the best suited version.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Implement functionality as specified in the Celestial architecture simulator in HLS (System C/C++). Negotiate changes with architects as needed to meet performance goals.
• Author detailed design documents.
• Perform power, area, and performance trade-off analysis.
• Collaborate with the DV team and review test plans to ensure bug free designs.
• Drive coverage closure of your designs.

QUALIFICATIONS:

• 5+ years of RTL design experience (Verilog, SystemVerilog, digital microarchitecture).
• Extensive experience coding C/C++.
• Experience with High Level Synthesis for ASICs or FPGAs.
• Knowledge of basic processor architecture.
• Experience with full ASIC design cycle (spec through bring-up) preferred.
• BS plus 7 years relevant experience. MS preferred.

Location: San Francisco Bay Area or Orange County, CA

For California location:

As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $155,000.00 - $175,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.