Address
Form of workat Space Dynamics Laboratory in North Logan, Utah, United States
Job DescriptionJob ID 15498
The Space Dynamics Laboratory is seeking a skilled, mid-level or more experienced engineer to support FPGA firmware development, assessment, validation of government critical systems. The selected candidate will be involved in all aspects of FPGA development, including architecture, simulation, implementation, timing closure, and testing. The selected candidate must be able to work as part of an FPGA team, supporting a larger engineering design from concept to integration and test. SDL offers competitive salaries and fantastic benefits, including:+ Flexible work schedules that fit your style-every Friday off, every other Friday off, possible work from home days, or simply traditional hours
+ Generous paid leisure and sick leave, ensuring you never miss a special event
+ A 14.2% employer retirement contribution into a 401(a) account-no matching required!
+ Favorable company locations with average commute times of less than 15 minutes
+ Utah State University undergraduate tuition discounts of 50%, full reimbursement for graduate tuition, and free course audits for employees and dependents meeting eligibility requirements
+ High-quality, low-cost health, dental, and life insurance
+ A great, highly educated team that works together to solve some of the most fascinating problems on (and off) our planet
+ We are a growing company that maintains both a family feel and high retention rate with over 90% job satisfaction
+ Relocation assistance available for most positions
Required Qualifications:+ BS degree in electrical engineering, computer science, or related field
+ Minimum of three years of experience designing, simulating, implementing, performing timing closure, testing, debugging, and delivering FPGA-based digital electronics in VHDL, Verilog, P4 or similar firmware development languages and development tools
+ Experience with FPGA debugging tools and hardware troubleshooting equipment
+ Experience in specifying, selecting, and implementing FPGA support peripherals devices
+ Experience with power management/optimization strategies.
+ Familiarity with error mitigation/correction techniques
+ Demonstrated experience completing a project from requirement definition to integration and test
+ Must be a U.S. citizen and be able to obtain a U.S. Government Security Clearance.
Preferred Qualifications:+ MS degree preferred
+ Six years of relevant experience
+ Experience with printed wiring assembly design rules as they relate to high-speed digital logic design concepts, static timing analysis, and the process by which timing closure is achieved in a design
+ Hardware security experience including familiarity with securing FPGAs, secure boot, CRCs, side-channel attacks or prevention, malware protection, and securing design from IP theft.
+ Previous work in threat modeling
+ Past experience protecting data to ensure confidentiality, integrity, authenticity, and non-repudiation
SDL supports a variety of missions, including NASA's vision to reveal the unknown for the benefit of humankind and the Department of Defense's aim to protect our Nation on the ground, in the air, and in space. Our sensors, satellites, software systems, and science and engineering play an essential role in some important missions you've heard of, and others that you haven't. Join our team in our seventh decade of delivering mission success. For questions or assistance with the application process or the DoD SkillBridge program, please contact employment@sdl.usu.edu. EOE including Disability and VetPowered by JazzHR
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