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Job Description:
Foveros direct is one of Intel's upcoming packaging technology that uses hybrid bonding to enable 3D stacking of wafers. In specific the Wafer level Integration of Foveros direct spans fab integration: via and metallization layers , bumping, reveal, die-prep, die attach through hybrid bond and 3D stacking. Foveros direct Wafer level Integration engineer is responsible driving the technology development in all these respective areas. It is an exciting opportunity to enable Intel's roadmap with best in class technology offerings.
Responsibilities included but not limited to the followings:
The candidate should also exhibit the following behavioral traits:
Qualifications:
For information on Intel's immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information.
You must possess the below requirements to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Preferred Qualifications:
3+ years of experience in the following:
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
Foveros direct is one of Intel's upcoming packaging technology that uses hybrid bonding to enable 3D stacking of wafers. In specific the Wafer level Integration of Foveros direct spans fab integration: via and metallization layers , bumping, reveal, die-prep, die attach through hybrid bond and 3D stacking. Foveros direct Wafer level Integration engineer is responsible driving the technology development in all these respective areas. It is an exciting opportunity to enable Intel's roadmap with best in class technology offerings.
Responsibilities included but not limited to the followings:
- Lead the focus teams to develop technology.
- Lead Task Forces and working groups to solve integrated problems.
- Engage with key partners such as LTD, AFO, product design teams and ATTD stakeholders such as OATD-F, CATD, MTD, ADTS, xCC, QnR to deliver holistic solutions to the problems.
The candidate should also exhibit the following behavioral traits:
- Demonstrate communication and presentation skills.
- Demonstrate leadership skills and willingness to work with teams spread across different geographies and organizations
- Role model ONE INTEL culture.
- Demonstrate fast learning skills to understand new concepts related to diverse fields and apply them on the job to solve complex problems.
Qualifications:
For information on Intel's immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information.
You must possess the below requirements to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
- Candidate must possess a Bachelor's Degree with 4+ years of experience OR
- Master's Degree with 3+ years of experience OR
- PhD degree in Chemical Engineering or Materials Science or Physics.
Preferred Qualifications:
3+ years of experience in the following:
- Focus on fundamental understanding of SI processing.
- Process integration experience.
- Knowledge of NPI methodology DOE and statistical Process control.
- Rudimentary knowledge of characterization techniques such as CSAM, Xray, XPS, FTIR, SEM, EDX.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
