Ecad Designer/ Pcb Designer

This role will be responsible for the execution of PWB layout for RF, Power, Analog and Mix Signal used within a Magnetic Resonance (MR) system. The candidate will leverage knowledge of design techniques and communication standards to ensure a quality product. This is not a remote position given the nature of lab co-work and local communication is expected for candidate to executein person.

Job Responsibilities

• Packaging circuit boards into mechanical enclosures and assemblies leveraging Cadence Design tools and IPC standards.
• Guide engineers in component selection, placement, stack-up and material cost, routing, in-circuit test point location, artwork generation, assembly drawing creation, manufacturing documentation, Clienthival and configuration control
• Work with global suppliers and create design outputs with a global team
• Review external supplier layout designs to ensure high quality, as needed
• Institutionalize operating mechanisms that ensure standardization of work across multiple teams
• Utilizing independent judgement, construct, evaluate and improve complex engineering problem statements and promote creative solutions to improve engineering efficiency and outcomes.
• Take ownership for business objectives including delivery, EHS, productivity, cost management, serviceability, quality.
• Little to no direction is given in execution of job-related activities.
• Comply with EHS regulations and policies.

Required Qualifications:

• Associates degree or equivalent in electronics technology
• Minimum of 4 years' experience with complex analog, power, high speed digital, or RF PWB designs
• Demonstrated teamwork, coordination, and communication skills both locally and globally
• Demonstrated IPC PWB design principles knowledge
• Demonstrated ability to lead and supervise a team of eCAD designers or external vendors.
• Demonstrated experience with circuit stack-ups and routing with 2 to 14+ layers
• Experience with Cadence CAD capture and design tools
• Demonstrated experience with micro-vias, very fine pitch devices, and high-density processors/FPGAs (> 1000 contact BGAs)
• Demonstrated experience with signal integrity constraints management
• Experience with Valor design checks