DFT Timing Engineer

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THE ROLE:
As a Design-for-Testability (DFT) Timing Engineer, you should have extensive DFT shift/capture, various IP/modes and different PVT corner timing closure experiences. You will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, IP teams, Product Engineers and Program Management to ensure successful and timely project completion.
THE PERSON:
As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. You will work closely with architecture, IP design, SoC implementation team, Design Verification team and physical design team to achieve first pass silicon success. You should be able to work efficiently within a team environment and drive tasks to completion, all while demonstrating excellent oral, written and interpersonal communication skills!
KEY RESPONSIBILITIES:

• Basic understanding of Jtag, boundary scan, P1500, design for debug, SMS, scan, Tessent edt compression logic, SSN, hierarchical scan (INTEST/EXTEST), clock gating, power gating, ISO control
• Understanding of PD floorplan, scan/DFX repeaters, clock/reset structure, DFX for DDR/PHY/PCIE, FUSE, source synchronous bus
• With the above knowledges and design bounding box, create scan shift mode SDC, capture mode SDC (embedded in functional mode) and special timing for design specific modes
• Coordinate with IP team, DFX central team, SoC team, PD team, CAD team and library team to review SDC, analyze PrimeTime violation reports and provide feedback
• Ensure scan shift clock, Jtag clock, boundary scan clock and SMS clock meet target frequencies
• Ability to debug constraint issues and analyze timing violations related to setup/hold/clock skew/clock crossing/MCP/False path/settings, etc.
• Drive timing checklist and timing closure to tapeout with high quality and on time delivery

PREFERRED EXPERIENCE:

• DFT architecture and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, PHY loopback, etc)
• Expert in Synopsys PrimeTime, Perl/TCL/Shell scripting and Verilog RTL and netlist
• Prior experience and exposure to DFT timing closure is critical
• Must have good communication skills and the ability to work in a worldwide team environment
• Knowledge & experience of low power concepts, clock gating, power gating is a plus
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

ACADEMIC CREDENTIALS:

• BSEE/MSEE Electrical Engineering or Computer Engineering

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At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.