Job description
- Develop verification plans in coordination with design leads and architects - Direct team in creation and executing of verification plan - Own end to end validation of various CPU components and flows - Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and enhance test environment to target coverage holes - Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog, C/C++), and logic simulators to verify complex designs and create verification infrastructure
Address
Beaverton, OR
