Chipsets Senior IO Designer

Job Details:
Job Description:
Seize the opportunity to work with the team responsible for supporting all aspects of IO, circuit design, electrical design, and technology for Chipsets Silicon Group (CSG) products. This position is in the Chipset Ingredients Circuit Design Team which is part of CSG which is within Intel's Design Engineering Group (DEG).
As a Chipsets Senior I/O Designer, a typical day may include, but is not limited to:

• Defining and driving portions of the CSG IO leadership roadmap
• Working with key stakeholders with various planning, architecture and customer facing teams
• Developing executable and affordable strategies to achieve successful product implementation of the IO roadmap.
• Ensuring solutions are competitive and deliver industry leading capabilities.
• Rigorously engage and drive technical oversight of all suppliers, both within Intel and external third-party suppliers to ensure technical excellence and high-quality IO solutions for CSG products.
• Participating and leading technical task forces and strategic initiatives as makes sense.
• Participating in system level debug forums and task forces to ensure Intel product success.
• Providing technical mentoring and coaching the organization's junior engineers

As a successful candidate you must possess

• The ability to work well in a matrixed team environment and a multi-site international organization structure.
• Organizing skills
• The ability to collaborate.
• Passion for design/tools and methodology
• The ability to meet their commitments.
• The ability to make a difference through technology

Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor's degree in electrical engineering or computer engineering with over 6+ years of experience or a master's degree in electrical engineering or computer Engineering or any STEM Degree with over 4+ years of experience
6+ years of directly relevant CMOS silicon design experience in the any of the following:

• High-Speed IO design specifically with PCIex, USB4, USB3.x, SATAx, UFS, MIPI-MPHY/CPHY/DPHY and USB2 IO interfaces including PHY architecture, I/O protocol, circuit implementation, and platform level aspects.
• SoC level design of clock generation, power delivery, physical design, and chip planning

Preferred Qualifications:

• Knowledge of PHY layer to Controller/Protocol Layer interaction for different IO protocols e.g. RMMI for MIPI MPHY, PPI for MIPI DPHY, UTMI/UTMI+ for USB etc...
• Experience withscripting language like Python/PowerShell/Perl/Ruby
• Strategic planning and influencing at product level or IO IP roadmap level
• Hands-on in lab debug of the above-mentioned IO protocols
• Platform level clocking, power delivery, and signal integrity
• Designing on Intel and external foundry processes
• Influencing and participating in industry IO standards bodies

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$139,480.00-$209,760.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.