Cad Research Intern.

at Intel in Boise, Idaho, United States

Job Description

As a CAD Research Intern in the Design Enablement Test Chip Engineering (TCE) group, you will be responsible for the research and development of CAD software tools and flows, methodologies, and processes to support the design of Intel's next generation process technology test chips.

Your responsibilities will include but not be limited to:

- Development of CAD software/flows that automate physical layout of E-Test Structure devices and connectivity, layout dummification, design verification within a customized physical design framework.

- Definition of process design rules to make designs conform to process requirements.

- Collaborating with other manufacturing groups to define test structure designs.

- Troubleshoot design and DRC verification issues with complex physical designs flows and tools.

- Develop software to increase automation and productivity.

The candidate is expected to work closely with the team but carry out research, development, and test tasks with minimal supervision.

This is a remote internship position for 3+ months and compensation will be given accordingly.

\#DesignEnablement

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must be pursuing a PhD degree in Electrical, Computer science, or other related engineering discipline.

6+ months of experience in following areas:

- One of the following: Python, Perl, Tcl, SKILL, C++.

- Solving problems using efficient computer algorithm and effective programming techniques.

- UNIX/Linux or Shell.

- CAD tools for schematic entry, circuit simulation, custom layout, and design/layout verification, from vendors such as Cadence, Synopsys, and Siemens.

Preferred Qualifications:

1+ years of experience in the following:

- Physical design or CAD.

- Development of PCells or PyCells.

- Calibre SVRF and/or Cadence SKILL languages.

- Developing custom flows for EDA Tools using AI/ML concepts.

- Semiconductor device physics and process scaling.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, Colorado, New York, Washington, California: $63,000.00-$166,000.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.