Asic Memory Design Engineer

Job Description and Requirements
Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
ASIC Memory Design Engineer
We're looking for a Non-volatile Memory (NVM) design Engineer to join our team. Work directly with analog & digital experts to create customized digital solutions that will be fabricated, tested, and implemented into high volume applications.
We have mixed-signal product development in every node from 0.35um to 5nm and support all top tier foundries and customers. Come work with the leading innovator in this exciting field.
If you are a self-starting individual-contributor looking to expand their career potential, please contact us immediately.
Required Skills

• RTL / Verilog / System Verilog coding
• SOC design and digital tool flows execution
• Digital Verification
• Scripting
• Excellent written/verbal communication

Desired Experience / Skills

• Verification (model / verification test-bench / score-boarding creation and maintenance)
• Verification debug / root cause

Tools

• Custom Compiler / Design Compiler / Fusion Compiler
• VCS / Verdi / DVE
• Nanotime & Overall digital tool flows

Education

• Minimum of BSEE / CompE or equivalent

Experience

• New Graduates or 2+ years of industry experience in digital ASIC design

Roles & Responsibilities
Work collaboratively with analog, CAD, layout, and test teams in the following areas:

• IP
  • Create and validate RTL for IP, NVM controllers and test chip (SOC)
  • Synthesize, Place, and Route IP, NVM controller and test chip (SOC)
• Design Kit
  • Create behavioral model for NVM IP for customer implementation
  • Validate .lib and other digital views

The base salary range across the U.S. for this role is between $66,000.00 to$ 115,000.00 per hour. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.