Senior Design Verification Engineer

Who We Are

About Capgemini Engineering

World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet.

Capgemini Engineering is an integral part of the Capgemini Group, a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided every day by its purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse organization of over 340,000 team members in more than 50 countries. With its strong 55-year heritage and deep industry expertise, Capgemini is trusted by its clients to address the entire breadth of their business needs, from strategy and design to operations, fueled by the fast evolving and innovative world of cloud, data, AI, connectivity, software, digital engineering and platforms. The Group reported in 2021 global revenues of 18 billion.

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Capgemini discloses salary range information in compliance with state and local pay transparency obligations. The disclosed range represents the lowest to highest salary we, in good faith, believe we would pay for this role at the time of this posting, although we may ultimately pay more or less than the disclosed range and the range may be modified in the future. The disclosed range takes into account the wide range of factors that are considered in making compensation decisions including, but not limited to, geographic location, relevant education, qualifications, certifications, experience, skills, seniority, performance, sales or revenue-based metrics, and business or organizational needs. At Capgemini, it is not typical for an individual to be hired at or near the top of the range for their role. The base salary range for the tagged location is [$120,000-$150,000/yr].

This role may be eligible for other compensation including variable compensation, bonus, or commission. Full-time regular employees are eligible for paid time off, medical/dental/vision insurance, 401(k), and any other benefits to eligible employees.

Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, or any other form of compensation that is allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company's sole discretion, consistent with the law.

Senior Design Verification Engineer

Remote role

What you'll do:

• You will be working as Design Verification Engineer
• Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.  
• Develop test plans and coverage metrics from specifications and writing block and chip-level tests. 
• Create PERL/Python scripts to automate creating verification environments, tests generation and debugging. 
• Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers. 
• Create low power testcases using UPF or CPF to verify the desired power intent of the SoC. 
• Extensive experience debugging designs as well as creating simulation environments
• Triage and debug testbench simulation fails at both unit and top level
• Define, document, and implement a from-scratch UVM verification environment including agents and scoreboards
• Work with architects to determine the use-case scenarios to simulate

What you'll have:

• 10 years of experience in pre-silicon design verification
• Proficiency in C-shell scripting, Verilog-HDL & System Verilog.
• Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. 
• SOC Verification experience using ARM Cortex Microcontroller is required.
• Experience with advanced peripheral bus Verification IP's such as GPIO, UART, SPI, SW, JTAG, and I2C.
• Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful.
• Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
• Independent, self-motivated with good analytical & communication skills.
• UVM/SystemVerilog/Python/C /NCSIM

Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory, or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.

Click the following link for more information on your rights as an Applicant

http://www.capgemini.com/resources/equal-employment-opportunity-is-the-law