Pcb Layout Engineer jobs in California

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SENIOR ANALOG LAYOUT ENGINEER

Senior Layout Engineers/Leads are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS,...

CompanyHardware
AddressSan Diego, CA
CategoryInformation Technology
Date Posted 22 hours ago See detail

Senior Analog Layout Engineer New

Hardware

San Diego, CA

Senior Layout Engineers/Leads are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS,...

RFIC Layout Engineer

Hardware

Sunnyvale, CA

As a RF IC Layout Engineer, you will be a key member of a small RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.Responsibili...

IC Physical Layout Engineer

Hrl Laboratories

Malibu, CA

Based in Southern California with locations in Malibu, Calabasas, Westlake Village and Camarillo; HRL has been on the leading edge of technology, conducting pioneering research and advancing the state of the art. Within the range,...

IC Layout Engineer (Starlink)

Spacex

Sunnyvale, CA

Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations. Accurate...

Senior Layout & Rendering Engineer

Software And Services

Cupertino, CA

We want someone with a passion for quality and the desire to improve the web for both users and developers. This team works on Style, DOM, Paint, Layout, Rendering, Typography, SVG, and Scrolling.SPECIFIC JOB DUTIES WILL INCLUDE:...

Senior Mask Layout Design Engineer

Nvidia

Santa Clara, CA

$104,000 - $195,500 a year

Testchip Layout: Physical layout of SRAM periphery, datapath, and other specialized circuits on advanced foundry processes with early and unstable design environments. Methodology Development: Explore physical tradeoffs, optimize...