Engagement Director - Sr Dft Engineer

Who We Are

About Capgemini Engineering

World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet.

Capgemini Engineering is an integral part of the Capgemini Group, a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided every day by its purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse organization of over 340,000 team members in more than 50 countries. With its strong 55-year heritage and deep industry expertise, Capgemini is trusted by its clients to address the entire breadth of their business needs, from strategy and design to operations, fuelled by the fast-evolving and innovative world of cloud, data, AI, connectivity, software, digital engineering, and platforms. The Group reported 2021 global revenues of €18 billion.

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Capgemini discloses salary range information in compliance with state and local pay transparency obligations. The disclosed range represents the lowest to highest salary we, in good faith, believe we would pay for this role at the time of this posting, although we may ultimately pay more or less than the disclosed range and the range may be modified in the future. The disclosed range takes into account the wide range of factors that are considered in making compensation decisions including, but not limited to, geographic location, relevant education, qualifications, certifications, experience, skills, seniority, performance, sales or revenue-based metrics, and business or organizational needs. At Capgemini, it is not typical for an individual to be hired at or near the top of the range for their role. The base salary range for the tagged location is [$122,000-$200,000/yr].

This role may be eligible for other compensation including variable compensation, bonus, or commission. Full-time regular employees are eligible for paid time off, medical/dental/vision insurance, 401(k), and any other benefits to eligible employees.

Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, or any other form of compensation that is allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company's sole discretion, consistent with the law.

Engagement Director - Sr DFT Engineer

Remote Role

What you'll do:

• Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements
• Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation.
• Verify DFT circuitry and interface with other blocks, debug timing simulation issues.
• Closely work with physical design team to generate and validate timing constraints.
• Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning.
• Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC.
• Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage
• Ability to lead/manage a team, with active technical interaction with engineering teams

What you'll have:

• 10+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs.
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. Experience with Synopsys DFT Complier, Tetramax and VCS is required.
• Experience with TestMaxDFT, SMS, TestMaxAdvisor tool suite is a plus.
• Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics
• Hands-on expertise in writing System Verilog and VHDL
• Hands-on in Perl/Tcl/Python/Unix scripting
• Excellent analytical, and problem-solving skills
• 8+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE)
• Education: BSEE, in Electrical/Computer) OR (MSEE, in (Electrical/Computer)
• DFT/MEMBIST/TetraMax/Logicvision/TCL

Engagement Director - Sr DFT Engineer

Remote Role

What you'll do:

• Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements
• Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation.
• Verify DFT circuitry and interface with other blocks, debug timing simulation issues.
• Closely work with physical design team to generate and validate timing constraints.
• Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning.
• Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC.
• Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage
• Ability to lead/manage a team, with active technical interaction with engineering teams

What you'll have:

• 10+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs.
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. Experience with Synopsys DFT Complier, Tetramax and VCS is required.
• Experience with TestMaxDFT, SMS, TestMaxAdvisor tool suite is a plus.
• Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics
• Hands-on expertise in writing System Verilog and VHDL
• Hands-on in Perl/Tcl/Python/Unix scripting
• Excellent analytical, and problem-solving skills
• 8+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE)
• Education: BSEE, in Electrical/Computer) OR (MSEE, in (Electrical/Computer)
• DFT/MEMBIST/TetraMax/Logicvision/TCL

Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory, or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.

Click the following link for more information on your rights as an Applicant

http://www.capgemini.com/resources/equal-employment-opportunity-is-the